1. Field the Invention
The present invention relates to the field of computer memory and input/output circuits, and more particularly, to output preconditioning circuits or output precharge circuits.
2. Description of the Related Art
Synchronous SRAMs are often specified with a large capacitive load (50 pf-85 pF). Since charge is equal to capacitance times voltage (Q=C*V), a large capacitance (C) means that the output driver has to charge or discharge a large amount of charge. One way to reduce the amount of charge to be charged or discharged is to reduce the voltage swing V (i.e., V=VOH-VOL, in the normal case) for a given capacitive load where VOH is the maximum output swing level, and VOL is the minimum output swing level. In the past, attempts have been made to reduce this voltage swing V by preconditioning the output to certain intermediate level Vint such that VOH-V.sub.int is less than VOH-VOL, or V.sub.int -VOL is less than VOH-VOL. A smaller amount of charge results in a faster output delay for a given output driver and output load, and also reduces noise. Normally preconditioning is accomplished by sensing the voltage level of the output and by determining the direction of preconditioning. Then the preconditioning drivers drive the output to an intermediate level.
However, the problem with the prior art circuits is the response of preconditioning circuit to a very low Capacitive load. In this case, the output can start oscillating before the actual data arrives at the output. For example, if the output is low (i.e., the output is at the VOL level), the preconditioning circuit starts preconditioning the output towards the VOH level. Since the capacitive load is low, the output driver preconditions the output to VOH level very fast. Since the actual data has not arrived yet, the preconditioning circuit senses the output at the VOH level and starts driving the output from the VOH level to the VOL level. Thus, the output will oscillate until the actual data arrives. The preconditioning circuit is then shut off. Also, if the output is preconditioned up to the full TTL level (i.e., VOH or VOL), the advantage of preconditioning vanishes as the amount of charge to charge or discharge is not reduced.
The implementation of output preconditioning has been described in two papers. A paper titled "A 14 ns 0.35 .mu.m 4M6 CMOS SRAM with an Output Preconditioning Circuit" by Fumio Miyaji of ULSI R & D Group of SONY Corporation describes a preconditioning circuit without an output level latch circuit. This preconditioning circuit is mainly used for 3 V output power supply and uses a pseudo clamping scheme. The circuit uses a p-channel diode for VOL clamping and an n-channel diode for VOH clamping. For 3 V output power supplies, an n-channel VOH clamp should be sufficient, but for 5 V power supplies, the n-channel clamp will result in preconditioning of the output to almost VOH level, and thereby the scheme does not provide the benefit of preconditioning the output for 5 V power supplies.
In a paper titled "A 16 ns 512K.times.8 CMOS SRAN With Power Saving and Output Buffer Noise Reduction Features" by Larry Childs of Memory Product Division of Motorola Inc., an output preconditioning circuit is proposed to control noise. This paper, however, does not suggest the use of either output level clamping or output level latching described and claimed in the present invention.
The present invention solves the various problems mentioned above through innovative circuit design techniques.